Consider the following Verilog module.

module guess (data, cond, result);

input [7:0] data;

input [1:0] cond;

output reg result;

always @(data)

begin

if (cond == 2’b00)

result = |data;

else

result = ~^data;

end

endmodule

Which of the following are true when the module is synthesized? (multiple choices)

None of the above

Suspend simulation

End simulation

Exit simulator

9

Invalid expression

6

27

A. 6’b111000

B. 6’b011000

C. None of the above

D. 6’b111111

It cannot be determined exactly how many times the value of ‘x’ will be printed

The simulation will print the current value of ‘x’ 15-times

The simulation will print the current value of ‘x’ 13-times

The simulation will always display 15 as the value of ‘x’

A. 00100110

B. 00111110

C. 01111110

D. None of these

All of the above

A variable index used at the RHS of an “assign” statement generates a multiplexer whereas usage of it at the LHS results in a decoder

The “assign” statement can be used to implement both combinational as well as sequential circuits

The use of conditional operator in an “assign” statement always results in a multiplexer

100ns/110ps

1ns/1ps

100ns/100ps

10ns/1ps