What will the following code segment generate on synthesis, assuming that the four variables data0, data1, data2 and data3 map into four latches/flip-flops?

always @(posedge clock)

begin

data3 = din;

data2 = data3;

data1 = data2;

data0 = data1;

end

If A = 4b001x and B = 4b1011, then result of A + B will be

None of the above

Suspend simulation

End simulation

Exit simulator

9

Invalid expression

6

27

It cannot be determined exactly how many times the value of ‘x’ will be printed

The simulation will print the current value of ‘x’ 15-times

The simulation will print the current value of ‘x’ 13-times

The simulation will always display 15 as the value of ‘x’

A. 6’b111000

B. 6’b011000

C. None of the above

D. 6’b111111

A. 00100110

B. 00111110

C. 01111110

D. None of these

All of the above

A variable index used at the RHS of an “assign” statement generates a multiplexer whereas usage of it at the LHS results in a decoder

The “assign” statement can be used to implement both combinational as well as sequential circuits

The use of conditional operator in an “assign” statement always results in a multiplexer

100ns/110ps

1ns/1ps

100ns/100ps

10ns/1ps